Priority is claimed to Korean Patent Application No. 10-2005-0019579, filed on Mar. 9, 2005 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Disclosure
The present disclosure relates to nano wires and a method of manufacturing the same, and more particularly, to silicon nano wires made by accurately controlling the size and distribution of nucleation regions for forming the nano wires when forming silicon nano wires, and a method of manufacturing the same.
2. Description of the Related Art
Nano wires are currently being widely researched, and are a next-generation technology used in various devices such as optical devices, transistors, and memory devices. Materials used in nano wires include silicon, zinc oxide, and gallium nitride, which is a light emitting semiconductor. The nano wire manufacturing technique is sufficiently developed to be used for altering of the length and width of nano wires.
Quantum dots or nano light emitting devices using quantum dots are used in conventional nano light emitting (EL) devices. Organic EL devices using quantum dots have high radiative recombination efficiency but low carrier injection efficiency. GaN LEDs, which use quantum wells, have relatively high radiative recombination efficiency and carrier injection efficiency. However, it is very difficult to produce GaN LED on a large area due to a defect caused by the difference in the crystallization structures of the GaN LED and a commonly used sapphire substrate, and thus the manufacturing costs of GaN LEDs are relatively high. A nano light emitting device using nano wires has very high radiative recombination efficiency and relatively high carrier injection efficiency. In addition, the manufacturing process of a nano light emitting device is simple and a nano light emitting device can be formed to have a crystallization structure that is practically similar to that of a substrate, and thus it is easy to form the nano light emitting device in a large area.
FIGS. 1A through 1D are cross-sectional views illustrating a vapor-liquid-solid (VLS) method, which is a conventional method of manufacturing nano wires.
Referring to FIG. 1A, first, a substrate 11 is provided. The substrate 11 may be a commonly used silicon substrate.
Thereafter, referring to FIG. 1B, a metal layer 12 is formed on top of the substrate 11 by spreading a metal such as Au.
Then, referring to FIG. 1C, the resultant structure is thermally processed at approximately 500° C. As a result, materials in the metal layer 12 are agglomerated, thereby forming catalysts 13. The sizes of the catalysts 13 are irregular.
After forming the catalysts 13, nano wires 14 are formed where the catalysts 13 are formed using the catalysts 13 as nucleation regions, as illustrated in FIG. 1D. The nano wires 14 are formed by supplying, for example, silane (SiH4), which is a compound of silicon and hydrogen, to the catalysts 13 to induce nucleation of Si of silane at the locations where the catalysts 13 are formed. When supplying the silane, the nano wires 14 can continuously grow from the bottom of the catalysts 13, as illustrated in FIG. 1D.
As described above, nano wires with desired lengths can be easily formed by appropriately controlling the amount of supplied material gas such as silane. However, the growth of nano wires can be limited by the diameters and distribution of the catalysts, and thus it is difficult to accurately control the thicknesses and distribution of nano wires.